Intel gave the first glimpse of three packaging tech on its plan at a meeting on the sidelines of Semicon West. The most fascinating of the three may enter in the exascale supercomputer Intel is developing for the U.S. Division of Energy.
The trio of techniques aims to present Intel’s processors a brim at a time when advances in standard silicon scaling are slowing and getting costlier. They enter as rival TSMC extends its portfolio of chip stacks, and two consortia hope to set standards in the sector.
MDIO is the next-gen of Intel’s AIB, a bodily interface for stacking chips it released in 2018 as a part of a DARPA project. Intel claims MDIO is on the level of advances rival TSMC introduced in June. It needs to employ the interface in chip stacks beginning sometime in 2020; however, has not planned if it is going to make the spec open.
The most fascinating of the three new techniques is Co-EMIB. A mix of Intel’s newest 2D and 3D stacking strategies, it likely will see its first use as a way to connect GPU and CPU cores in the Aurora supercomputer Intel and Cray secured a $500 million offer to ship before the end of 2021.
Prototypes shown of Co-EMIB wafers and gadgets stacked 18 small die on a large one using the Foveros 3D method Intel announced in last December. Two of the units were then linked using four of its Embedded Multi-Die Interconnect Bridge (EMIB) links utilizing 45- and 55-mm bump pitches.
Intel has delivered as many as a million units employing EMIB in Stratix X FPGAs and Kaby Lake G, a built-in CPU or GPU module. In 2020, it’ll release Lakefield, an integrated notebook processor slated to be its first chip employing Foveros.
The third new possibility is thus far just a research project. Omni Directional Interconnect (ODI) is a 70mm thick vertical link for shipping power to a chip.