Back when Intel introduced the Skylake microarchitecture, Intel proceeded to rebalance the cache structure of its CPUs within the HEDT fleet. In keeping with Geekbench, a similar cache rebalancing may be coming to the forthcoming 10nm Tiger Lake cell CPUs.
Assuming Intel follows similar actions taken previously to the release of HEDT Skylake-X CPUs, Intel could proceed with the trend of Tiger Lake. In the case of Skylake-X, Intel lowered the amount of L3 cache in favor of elevated lower-latency L2 cache, although, with Tiger Lake-Y, Intel could bring improvements in each L1, L2, and L3 caches. Beforehand, mobile and desktop CPUs shared the same cache construction, however, with a redesign of the cache, Intel may carry increased efficiency to mobile CPUs.
Looking at the Geekbench report, the system in question is working a Tiger Lake-Y CPU and features four cores and eight threads. This chip features a considerably altered cache with a big 1.25MB of L2 cache per core, including as much as 5MB of total L2 cache. This quantity of L2 cache is a 400% improvement over its predecessor. Along with the numerous increase of L2 cache, Intel’s pattern CPU boasts a 50% L3 cache dimension improvement at a complete of 12MB.
The pattern CPU examined appears to beat a trade-off required with existing Skylake-X CPUs; increased L2 cache doesn’t come at the cost of reduced L3 cache, subsequently, efficiency increases throughout the board. Other enhancements anticipated from Tiger Lake include the introduction of PCIe 4.0, a characteristic currently out there exclusively to AMD’s X570 and TRX40 platforms, and Intel Xe iGPU’s 96 EUs.